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twindie ? 1.2v ddr4 sdram mt40a4g4 C 128 meg x 4 x 16 banks x 2 ranks mt40a2g8 C 64 meg x 8 x 16 banks x 2 ranks description the 16gb (twindie ? ) ddr4 sdram uses microns 8gb ddr4 sdram die (essentially two ranks of the 8gb ddr4 sdram). refer to microns 8gb ddr4 sdram data sheet for the specifications not in- cluded in this document. specifications for base part number mt40a2g4 correlate to twindie manufactur- ing part number mt40a4g4; specifications for base part number mt40a1g8 correlate to twindie manu- facturing part number mt40a2g8. features ? uses 8gb micron die ? two ranks (includes dual cs#, odt, and cke balls) ? each rank has 4 groups of 4 internal banks for con- current operation ? v dd = v ddq = 1.2v (1.14C1.26v) ? 1.2v v ddq -terminated i/o ? jedec-standard ball-out ? low-profile package ? t c of 0c to 95c C 0c to 85c: 8192 refresh cycles in 64ms C 85c to 95c: 8192 refresh cycles in 32ms options marking ? configuration C 128 meg x 4 x 16 banks x 2 ranks 4g4 C 64 meg x 8 x 16 banks x 2 ranks 2g8 ? fbga package (pb-free) C 78-ball fbga (9.5mm x 13mm x 1.2mm) die rev :a fse C 78-ball fbga (8.0mm x 12mm x 1.2mm) die rev :b nre ? timing C cycle time 1 C 0.750ns @ cl = 18 (ddr4-2666) -075e C 0.833ns @ cl = 16 (ddr4-2400) -083e C 0.833ns @ cl = 17 (ddr4-2400) -083 C 0.937ns @ cl = 15 (ddr4-2133) -093e C 0.937ns @ cl = 16 (ddr4-2133) -093 ? self refresh C standard none ? operating temperature C commercial (0c t c 95c) none ? revision :a :b note: 1. cl = cas (read) latency. table 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -075e 1 2666 18-18-18 13.5 13.5 13.5 -083e 2 2400 16-16-16 13.32 13.32 13.32 -083 2 2400 17-17-17 14.16 14.16 14.16 -093e 2133 15-15-15 14.06 14.06 14.06 -093 2133 16-16-16 15 15 15 notes: 1. backward compatible to 1600, cl = 11; 1866, cl = 13; 2133, cl = 15; and 2400, cl = 17. 2. backward compatible to 2133, cl = 15 (-093e). 16gb: x4, x8 twindie ddr4 sdram description pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 4096 meg x 4 2048 meg x 8 configuration 128 meg x 4 x 16 banks x 2 ranks 64 meg x 8 x 16 banks x 2 ranks bank group address bg[1:0] bg[1:0] bank count per group 4 4 bank address in bank group ba[1:0] ba[1:0] row address 128k a[16:0] 64k a[15:0] column address 1k a[9:0] 1k a[9:0] 16gb: x4, x8 twindie ddr4 sdram description pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
ball assignments and descriptions figure 1: 78-ball fbga ball assignments (top view) 1 2 3 4 6 7 8 9 5 v dd v pp v ddq v ssq v ss v dd v ss v dd v refca v ss reset_n v dd v ss v ssq v ddq dq0 dq4/nc v ddq c2/odt1 c0/cke1 we_n/a14 bg0 ba0 a6 a8 a11 v ssq v ddq v ss dq5/nc v ddq ck_c c1/cs1_n ras_n/a16 bg1 ba1 a5 a7 a13 v ssq zq v ddq v ssq v ss v dd rfu/ten v ss v dd v ss alert_n v pp v dd a b c d e f g h j k l m n a b c d e f g h j k l m n nf, nf/dm_n/ dbi_n/tdqs_t dq1 v dd dq3 dq7/nc ck_t cs_n cas_n/a15 a12/bc_n a3 a1 a9 a17/nc nf, nf/ tdqs_c dqs_c dqs_t dq2 dq6/nc odt cke act_n a10/ap a4 a0 a2 par notes: 1. see the fbga 78-ball descriptions table. 2. dark balls (with ring) designate balls that are specific to controlling the second die of the twindie package when compared to a monolithic package. 3. a comma , separates the configuration; a slash / defines a selectable function. for example: ball a7 = nf, nf/dm_n/dbi_n/tdqs_t where nf applies to the x4 configuration only. nf/dm_n/dbi_n/tdqs_t applies to the x8 configuration only and is selectable be- tween nf, dm_n, dbi_n, or tdqs_t via mrs. 16gb: x4, x8 twindie ddr4 sdram ball assignments and descriptions pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 3: fbga 78-ball descriptions symbol type description a[17:0] input address inputs: provide the row address for activate commands and the col- umn address for read/write commands to select one location out of the memo- ry array in the respective bank. (a10/ap, a12/bc_n, we_n/a14, cas_n/a15, ras_n/ a16, have additional functions; see individual entries in this table). the address inputs also provide the op-code during the mode register set command. a16 is used on some 8gb and 16gb parts, and a17 is only used on some 16gb parts. a10/ap input auto precharge: a10 is sampled during read and write commands to deter- mine whether auto precharge should be performed to the accessed bank after a read or write operation (high = auto precharge; low = no auto precharge). a10 is sampled during a precharge command to determine whether the pre- charge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by the bank group and bank ad- dresses. a12/bc_n input burst chop: a12/bc_n is sampled during read and write commands to deter- mine if burst chop (on-the-fly) will be performed. (high = no burst chop; low = burst-chopped). see the command truth table. act_n input command input: act_n indicates an activate command. when act_n (along with cs_n) is low, the input pins ras_n/a16, cas_n/a15, and we_n/a14 are trea- ted as row address inputs for the activate command. when act_n is high (along with cs_n low), the input pins ras_n/ a16, cas_n/a15, and we_n/a14 are treated as normal commands that use the ras_n, cas_n, and we_n signals. see the command truth table. ba[1:0] input bank address inputs: define the bank (within a bank group) to which an acti- vate, read, write, or precharge command is being applied. also determines which mode register is to be accessed during a mode register set command. bg[1:0] input bank group address inputs: define the bank group to which a refresh, acti- vate, read, write, or precharge command is being applied. also determines which mode register is to be accessed during a mode register set command. bg[1:0] are used in the x4 and x8 configurations. c0/cke1, c1/cs1_n, c2/odt1 input stack address inputs: these inputs are used only when devices are stacked; that is, 2h, 4h, and 8h stacks for x4 and x8 configurations (these pins are not used in the x16 configuration). ddr4 will support a traditional dual-die package (ddp), which uses these three signals for control of the second die (cs1_n, cke1, odt1). ddr4 is not expected to support a traditional quad-die package (qdp). for all other stack configurations, such as a 4h or 8h, it is assumed to be a single- load (master/slave) type of configuration where c0, c1, and c2 are used as chip id selects in conjunction with a single cs_n, cke, and odt. ck_t, ck_c input clock: differential clock inputs. all address, command, and control input signals are sampled on the crossing of the positive edge of ck_t and the negative edge of ck_c. 16gb: x4, x8 twindie ddr4 sdram ball assignments and descriptions pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 3: fbga 78-ball descriptions (continued) symbol type description cke input clock enable: cke high activates, and cke low deactivates, the internal clock signals, device input buffers, and output drivers. taking cke low provides pre- charge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self refresh exit. after v refca has become stable during the power-on and initialization sequence, it must be maintained during all operations (including self refresh). cke must be maintained high throughout read and write accesses. input buffers (exclud- ing ck_t, ck_c, odt, reset_n, and cke are disabled during power-down. input buffers (excluding cke and reset#) are disabled during self refresh. cs_n input chip select: all commands are masked when cs_n is registered high. cs_n pro- vides for external rank selection on systems with multiple ranks. cs_n is consid- ered part of the command code. dm_ns input input data mask: dm_n is an input mask signal for write data. input data is masked when dm is sampled low coincident with that input data during a write access. dm is sampled on both edges of dqs. dm is not supported on x4 configu- rations. ldm_n is associated with dq[7:0]. the dm, dbi, and tdqs functions are enabled by mode register settings. see the data mask (dm) section. odt input on-die termination: odt (registered high) enables termination resistance in- ternal to the ddr4 sdram. when enabled, odt (r tt ) is applied only to each dq, dqs_t, dqs_c, dm_n/dbi_n/tdqs_t, and tdqs_c signal for the x4 and x8 configu- rations (when the tdqs function is enabled via mode register). the odt pin will be ignored if the mode registers are programmed to disable r tt . par input parity for command and address: this function can be enabled or disabled via the mode register. when enabled, the parity signal covers all command and ad- dress inputs, including ras_n/a16, cas_n/a15, we_n/a14, a[17:0], a10/ap, a12/ bc_n, ba[1:0], bg[1:0], c0/a18, c1/a19, c2/a20. control pins not covered by the parity signal are cs_n, cke, and odt. unused address pins that are density- and configuration-specific should be treated internally as 0s by the dram parity log- ic. ras_n/a16, cas_n/a15, we_n/a14 input command inputs: ras_n/a16 , cas_n/a15, and we_n/a14 (along with cs_n and act_n) define the command and/or address being entered. see the act_n de- scription in this table. reset_n input active low asynchronous reset: reset is active when reset_n is low, and in- active when reset_n is high. reset_n must be high during normal operation. reset_n is a cmos rail-to-rail signal with dc high and low at 80% and 20% of v dd ; that is, 960 mv for dc high and 240 mv for dc low. ten input connectivity test mode: ten is active when high and inactive when low. ten must be low during normal operation. ten is a cmos rail-to-rail signal with dc high and low at 80% and 20% of v dd (960mv for dc high and 240mv for dc low). 16gb: x4, x8 twindie ddr4 sdram ball assignments and descriptions pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 3: fbga 78-ball descriptions (continued) symbol type description dq i/o data input/output: bidirectional data bus. dq represents dq[3:0], and dq[7:0] for the x4, and x8, respectively. if write crc is enabled via mode register, the write crc code is added at the end of data burst. any one or all of dq0, dq1, dq2, and dq3 may be used to monitor the internal v ref level during test via mode register setting mr[4] a[4] = high, training times change when enabled. during this mode, r tt value should be set to high-z. this measurement is for veri- fication purposes and is not an external voltage supply pin. dbi_n i/o dbi input/output: data bus inversion. dbi_n is an input/output signal used for data bus inversion in the x8 configuration. dbi_n is associated with dq[7:0]. the dbi feature is not supported on x4 configurations. dbi can be configured for both read (output) and write (input) operations depending on the mode regis- ter settings. the dm, dbi, and tdqs functions are enabled by mode register set- tings. see the data bus inversion (dbi) section. dqs_t, dqs_c i/o data strobe: output with read data, input with write data. edge-aligned with read data, centered-aligned with write data. for the x4 and x8 configurations, dqs corresponds to the data on dq[3:0] and dq[7:0] respectively. ddr4 sdram supports a differential data strobe only and does not support a single-ended data strobe. alert_n output alert output: this signal allows the dram to indicate to the system's memory controller that a specific alert or event has occurred. alerts will include the com- mand/address parity error and the crc data error when either of these functions is enabled in the mode register. tdqs_t, tdqs_c output termination data strobe: tdqs_t and tdqs_c are used by x8 drams only. when enabled via the mode register, the dram will enable the same r tt termi- nation resistance on tdqs_t and tdqs_c that is applied to dqs_t and dqs_c. when the tdqs function is disabled via the mode register, the dm/tdqs_t pin will provide the data mask (dm) function, and the tdqs_c pin is not used. the tdqs function must be disabled in the mode register for the x4 configuration. the dm function is supported only in x8 configuration. v dd supply power supply: 1.2v 0.060v. v ddq supply dq power supply: 1.2v 0.060v. v pp supply dram activating power supply: 2.5v -0.125v / +0.250v. v refca supply reference voltage for control, command, and address pins. v ss supply ground. v ssq supply dq ground. zq reference reference ball for zq calibration: this ball is tied to an external 240 resistor (rzq), which is tied to v ssq . note that this ball is shared by two dram devices. as a result, zq calibration operations need to be carried out separately so that cor- rect values are achieved. rfu C reserved for future use. nc C no connect: no internal electrical connection is present. nf C no function: may have internal connection present, but has no function. 16gb: x4, x8 twindie ddr4 sdram ball assignments and descriptions pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
functional description the twindie ddr4 sdram is a high-speed, cmos dynamic random access memory device internally configured as two 16-bank ddr4 sdram devices. although each die is tested individually within the dual-die package, some twindie test results may vary from a like-die tested within a monolithic die package. the ddr4 sdram uses a double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o balls. a single read or write access consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the inter- nal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o balls. the differential data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the ddr4 sdram input receiver. dqs is center-aligned with data for writes. the read data is transmitted by the ddr4 sdram and edge-aligned to the data strobes. read and write accesses to the ddr4 sdram are burst-oriented. accesses start at a se- lected location and continue for a programmed number of locations in a programmed sequence. operation begins with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the address bits (including cs n #, ba n , and a n ) registered coincident with the read or write command are used to select the rank, bank, and starting column location for the burst access. this data sheet provides a general description, package dimensions, and the package ballout. refer to the micron monolithic ddr4 data sheet for complete information re- garding individual die initialization, register definition, command descriptions, and die operation. industrial temperature the industrial temperature (it) option, if offered, requires that the case temperature not exceed C40c or 95c. jedec specifications require the refresh rate to double when t c exceeds 85c; this also requires use of the high-temperature self refresh option. addi- tionally, odt resistance, i dd values, some i dd specifications and the input/output im- pedance must be derated when t c is < 0c or > 95c. see the ddr4 monolithic data sheet for details. 16gb: x4, x8 twindie ddr4 sdram functional description pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
functional block diagrams figure 2: functional block diagram (128 meg x 4 x 16 banks x 2 ranks) par ten reset ck ck# dq[3:0] dqs, dqs# dm a[13:0], act_n, we_n/a14, cas_n/a15, ras_n/a16, ba[1:0], bg[1:0] cs0# cke0 odt0 rank 0 (128 meg x 4 x 16 banks) rank 1 (128 meg x 4 x 16 banks) cs1# cke1 odt1 alert_n zq figure 3: functional block diagram (64 meg x 8 x 16 banks x 2 ranks) tdqs# ten par reset ck ck# dq[7:0] dqs, dqs# dbi/dm/tdqs a[13:0], act_n, we_n/a14, cas_n/a15, ras_n/a16, ba[1:0], bg[1:0] cs0# cke0 odt0 cs1# cke1 odt1 zq alert_n rank 1 (64 meg x 8 x 16 banks) rank 0 (64 meg x 8 x 16 banks) 16gb: x4, x8 twindie ddr4 sdram functional block diagrams pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical specifications C leakages table 4: input and output leakages symbol parameter min max units notes i in input leakage current any input 0v v in v dd , v ref pin 0v v in 1.1v (all other pins not under test = 0v) C4 4 a 1 i vrefca v ref supply leakage current (all other pins not under test = 0v) C4 4 a 2 i zq input leakage on zq pin C6 6 a i ten input leakage on ten pin C8 8 a i ozpd output leakage: v out = v ddq C 10 a 3 i ozpu output leakage: v out = v ssq C100 C a 3, 4 notes: 1. any input 0v < v in < 1.1v 2. v refca = v dd /2, v dd at valid level. 3. dq are disabled. 4. odt is disabled with the odt input high. temperature and thermal impedance it is imperative that the ddr4 sdram devices temperature specifications, shown in the following table, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in main- taining the proper junction temperature is using the devices thermal impedances cor- rectly. the thermal impedances listed in table 6 (page 10) apply to the current die re- vision and packages. incorrectly using thermal impedances can produce significant errors. read micron technical note tn-00-08, thermal applications, prior to using the values listed in the thermal impedance table. for designs that are expected to last several years and require the flexibility to use several dram die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. the ddr4 sdram devices safe junction temperature range can be maintained when the t c specification is not exceeded. in applications where the devices ambient tem- perature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. 16gb: x4, x8 twindie ddr4 sdram electrical specifications C leakages pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 5: thermal characteristics notes 1C3 apply to entire table parameter symbol value units notes operating temperature t c 0 to 85 c 0 to 95 c 4 notes: 1. max operating case temperature t c is measured in the center of the package, as shown below. 2. a thermal solution must be designed to ensure that the device does not exceed the maximum t c during operation. 3. device functionality is not guaranteed if the device exceeds maximum t c during operation. 4. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate. the use of self refresh temperature (srt) or automatic self refresh (asr), if available, must be enabled. figure 4: temperature test point location test point length (l) width (w) 0.5 (w) 0.5 (l) table 6: thermal impedance package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) notes 78-ball rev a "fse" low conductivity 47.9 36.2 32.0 na 1.6 1 high conductivity 28.3 23.0 21.3 10.6 na 78-ball rev b "nre" low conductivity 53.5 41.5 37.0 na 1.5 1 high conductivity 33.2 27.4 25.6 20.2 na note: 1. thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. 16gb: x4, x8 twindie ddr4 sdram electrical specifications C leakages pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 5: thermal impedance 53.5 41.5 37.0 1.5 33.2 27.4 25.6 20.2 0 10 20 30 40 50 60 ja (0 m/s) ja (1 m/s) ja (2 m/s) jb jc thermal impedance (c/w) low conductivity test board high conductivity test board note: 1. all simulations are conducted per jedec standards. 16gb: x4, x8 twindie ddr4 sdram electrical specifications C leakages pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical characteristics C ac and dc output measurement levels single-ended outputs table 7: single-ended output levels parameter symbol ddr4-1600 to ddr4-3200 unit dc output high measurement level (for iv curve linearity) v oh(dc) 1.1 v ddq v dc output mid measurement level (for iv curve linearity) v om(dc) 0.8 v ddq v dc output low measurement level (for iv curve linearity) v ol(dc) 0.5 v ddq v ac output high measurement level (for output slew rate) v oh(ac) (0.7 + 0.15) v ddq v ac output low measurement level (for output slew rate) v ol(ac) (0.7 - 0.15) v ddq v note: 1. the swing of 0.15 v ddq is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of rzq/7 and an effective test load of 50 to v tt = v ddq . using the same reference load used for timing measurements, output slew rate for fall- ing and rising edges is defined and measured between v ol(ac) and v oh(ac) for single- ended signals. table 8: single-ended output slew rate definition description measured defined by from to single-ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) - v ol(ac) ]/ tr se single-ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) - v ol(ac) ]/ tf se figure 6: single-ended output slew rate definition tr se tf se v oh(ac) v ol(ac) single-ended output voltage (dq) 16gb: x4, x8 twindie ddr4 sdram electrical characteristics C ac and dc output measurement levels pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 9: single-ended output slew rate for r on = r zq /7 parameter symbol ddr4-1333 / 1866 / 2133 / 2400 /2666 unit min max single-ended output slew rate srq se 2 7 v/ns notes: 1. sr = slew rate; q = query output; se = single-ended signals 2. in two cases a maximum slew rate of 12v/ns applies for a single dq signal within a byte lane: ? case 1 is defined for a single dq signal within a byte lane that is switching into a cer- tain direction (either from high-to-low or low-to-high) while all remaining dq sig- nals in the same byte lane are static (they stay at either high or low). ? case 2 is defined for a single dq signal within a byte lane that is switching into a cer- tain direction (either from high-to-low or low-to-high) while all remaining dq sig- nals in the same byte lane are switching into the opposite direction (from low-to- high or high-to-low, respectively). for the remaining dq signal switching into the opposite direction, the standard maximum limit of 7 v/ns applies. differential outputs table 10: differential output levels parameter symbol ddr4-1600 to ddr4-3200 unit ac differential output high measurement level (for output slew rate) v oh,diff(ac) 0.3 v ddq v ac differential output low measurement level (for output slew rate) v ol,diff(ac) C0.3 v ddq v note: 1. the swing of 0.3 v ddq is based on approximately 50% of the static single-ended out- put peak-to-peak swing with a driver impedance of rzq/7 and an effective test load of 50 to v tt = v ddq at each differential output. using the same reference load used for timing measurements, output slew rate for fall- ing and rising edges is defined and measured between v ol,diff(ac) and v oh,diff(ac) for dif- ferential signals. table 11: differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v ol,diff(ac) v oh,diff(ac) [v oh,diff(ac) - v ol,diff(ac) ]/ tr diff differential output slew rate for falling edge v oh,diff(ac) v ol,diff(ac) [v oh,diff(ac) - v ol,diff(ac) ]/ tf diff 16gb: x4, x8 twindie ddr4 sdram electrical characteristics C ac and dc output measurement levels pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 7: differential output slew rate definition tr diff tf diff v oh,diff(ac) v ol,diff(ac) differential input voltage (dqs_t, dqs_c) table 12: differential output slew rate for r on = r zq /7 parameter symbol ddr4-1333 / 1866 / 2133 / 2400 / 2666 unit min max differential output slew rate srq diff 4 14 v/ns note: 1. sr = slew rate; q = query output; diff = differential signals. reference load for ac timing and output slew rate the effective reference load of 50 to v tt = v ddq and driver impedance of r zq /7 for each output was used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. r on nominal of dq, dqs_t and dqs_c drivers uses 34 ohms to specify the relevant ac timing paraeter values of the device. the maximum dc high level of output signal = 1.0 v ddq , the minimum dc low level of output signal = { 34 /( 34 + 50 ) } v ddq = 0.4 v ddq the nominal reference level of an output signal can be approximated by the following: the center of maximum dc high and minimum dc low = { ( 1 + 0.4 ) / 2 } v ddq = 0.7 v ddq . the actual reference level of output signal might vary with driver r on and refer- ence load tolerances. thus, the actual reference level or midpoint of an output signal is at the widest part of the output signals eye. 16gb: x4, x8 twindie ddr4 sdram electrical characteristics C ac and dc output measurement levels pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 8: reference load for ac timing and output slew rate timing reference point dq, dqs_t, dqs_c, dm, tdqs_t, tdqs_c ck_t, ck_c dut v tt = v ddq v ddq v ssq r tt = 50 16gb: x4, x8 twindie ddr4 sdram electrical characteristics C ac and dc output measurement levels pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical specifications C i cdd parameters table 13: ddr4 i cdd specifications and conditions (rev. a) note 1 applies to the entire table combined symbol individual die status bus width ddr4-2133 ddr4-2400 ddr4-2666 units i cdd0 i cdd0 = i dd0 + i dd2p + 3 x4, x8 83 93 tbd ma i cpp0 i cpp0 = i pp0 + i pp3n x4, x8 6 6 tbd ma i cdd1 i cdd1 = i dd1 + i dd2p + 3 x4, x8 98 108 tbd ma i cdd2n i cdd2n = i dd2n + i dd2p x4, x8 70 80 tbd ma i cdd2nt i cdd2nt = i dd2nt + i dd2p x4, x8 80 90 tbd ma i cdd2p i cdd2p = i dd2p + i dd2p x4, x8 50 60 tbd ma i cdd2q i cdd2q = i dd2q + i dd2p x4, x8 70 75 tbd ma i cdd3n i cdd3n = i dd3n + i dd2p x4, x8 80 85 tbd ma i cpp3n i cpp3n = i pp3n + i pp3n x4, x8 6 6 tbd ma i cdd3p i cdd3p = i dd3p + i dd2p x4, x8 60 70 tbd ma i cdd4r i cdd4r = i dd4r + i dd2p + 3 x4 163 178 tbd ma x8 178 183 tbd i cdd4w i cdd4w = i dd4w + i dd2p + 3 x4 163 178 tbd ma x8 178 193 tbd i cdd5b i cdd5b = i dd5b + i dd2p x4, x8 250 255 tbd ma i cpp5b i cpp5b = i pp5b + i pp3n x4, x8 33 33 tbd ma i cdd6n i cdd6n = i dd6n + i dd6n x4, x8 60 60 tbd ma i cdd6e i cdd6e = i dd6e + i dd6e x4, x8 70 70 tbd ma i cdd6r 2 i cdd6r = i dd6r + i dd6r x4, x8 50 50 tbd ma i cdd6a (25c) 2 i cdd6a = i dd6a + i dd6a x4, x8 40 40 tbd ma i cdd6a (45c) 2 i cdd6a = i dd6a + i dd6a x4, x8 50 50 tbd ma i cdd6a (75c) 2 i cdd6a = i dd6a + i dd6a x4, x8 70 70 tbd ma 16gb: x4, x8 twindie ddr4 sdram electrical specifications C i cdd parameters pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 13: ddr4 i cdd specifications and conditions (rev. a) (continued) note 1 applies to the entire table combined symbol individual die status bus width ddr4-2133 ddr4-2400 ddr4-2666 units i cdd7 i cdd7 = i dd7 + i dd2p + 3 x4 213 223 tbd ma x8 228 238 tbd i cpp7 i cpp7 = i pp7 + i pp3n x4, x8 18 18 tbd ma i cdd8 i cdd8 = i dd8 + i dd8 x4, x8 40 40 tbd ma notes: 1. i cdd values reflect the combined current of both individual die. i dd x represents individu- al die values. 2. i cdd6r and i cdd6a values are typical. 16gb: x4, x8 twindie ddr4 sdram electrical specifications C i cdd parameters pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 14: ddr4 i cdd specifications and conditions (rev. b) note 1 applies to the entire table combined symbol individual die status bus width ddr4-2133 ddr4-2400 ddr4-2666 units i cdd0 i cdd0 = i dd0 + i dd2p + 3 x4 68 71 tbd ma x8 73 76 tbd i cpp0 i cpp0 = i pp0 + i pp3n x4, x8 6 6 tbd ma i cdd1 i cdd1 = i dd1 + i dd2p + 3 x4 80 83 tbd ma x8 85 88 tbd i cdd2n i cdd2n = i dd2n + i dd2p x4, x8 58 59 tbd ma i cdd2nt i cdd2nt = i dd2nt + i dd2p x4, x8 70 75 tbd ma i cdd2p i cdd2p = i dd2p + i dd2p x4, x8 50 50 tbd ma i cdd2q i cdd2q = i dd2q + i dd2p x4, x8 55 55 tbd ma i cdd3n i cdd3n = i dd3n + i dd2p x4, x8 65 68 tbd ma i cpp3n i cpp3n = i pp3n + i pp3n x4, x8 6 6 tbd ma i cdd3p i cdd3p = i dd3p + i dd2p x4, x8 55 57 tbd ma x8 60 62 tbd i cdd4r i cdd4r = i dd4r + i dd2p + 3 x4 138 138 tbd ma x8 153 163 tbd i cdd4w i cdd4w = i dd4w + i dd2p + 3 x4 133 141 tbd ma x8 143 151 tbd i cdd5b i cdd5b = i dd5b + i dd2p x4, x8 275 275 tbd ma i cpp5b i cpp5b = i pp5b + i pp3n x4, x8 31 31 tbd ma i cdd6n i cdd6n = i dd6n + i dd6n x4, x8 60 60 tbd ma i cdd6e i cdd6e = i dd6e + i dd6e x4, x8 70 70 tbd ma i cdd6r 2 i cdd6r = i dd6r + i dd6r x4, x8 40 40 tbd ma i cdd6a (25c) 2 i cdd6a = i dd6a + i dd6a x4, x8 16 16 tbd ma i cdd6a (45c) 2 i cdd6a = i dd6a + i dd6a x4, x8 40 40 tbd ma 16gb: x4, x8 twindie ddr4 sdram electrical specifications C i cdd parameters pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 14: ddr4 i cdd specifications and conditions (rev. b) (continued) note 1 applies to the entire table combined symbol individual die status bus width ddr4-2133 ddr4-2400 ddr4-2666 units i cdd6a (75c) 2 i cdd6a = i dd6a + i dd6a x4, x8 60 60 tbd ma i cdd7 i cdd7 = i dd7 + i dd2p + 3 x4 188 193 tbd ma x8 198 203 tbd i cpp7 i cpp7 = i pp7 + i pp3n x4, x8 18 18 tbd ma i cdd8 i cdd8 = i dd8 + i dd8 x4, x8 50 50 tbd ma notes: 1. i cdd values reflect the combined current of both individual die. i dd x represents individu- al die values. 2. i cdd6r and i cdd6a values are typical. 16gb: x4, x8 twindie ddr4 sdram electrical specifications C i cdd parameters pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
package dimensions figure 9: 78-ball fbga die rev. a (package code fse) seating plane 0.1 a ball a1 id (covered by sr) ball a1 id a 0.3 0.05 1.1 0.1 6.4 ctr 9.5 0.1 0.8 typ 9.6 ctr 13 0.1 78x ?0.45 dimensions apply to solder balls post- reflow on ?0.33 nsmd ball pads. 0.8 typ 1 2 3 7 8 9 a b c d e f g h j k l m n notes: 1. all dimensions are in millimeters. 2. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). 16gb: x4, x8 twindie ddr4 sdram package dimensions pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 10: 78-ball fbga die rev. b (package code nre) 1.8 ctr nonconductive overmold 0.155 seating plane 0.12 a ball a1 id (covered by sr) ball a1 id a 0.34 0.05 1.1 0.1 6.4 ctr 8 0.1 0.8 typ 9.6 ctr 12 0.1 78x ?0.47 dimensions apply to solder balls post- reflow on ?0.42 smd ball pads. 0.8 typ 1 2 3 7 8 9 a b c d e f g h j k l m n notes: 1. all dimensions are in millimeters. 2. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-4000 www.micron.com/products/support sales inquiries: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. twindie is a trademark of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 16gb: x4, x8 twindie ddr4 sdram package dimensions pdf: 09005aef85fd40a1 ddr4_16gb_x4_x8_2cs_twindie.pdf - rev. d 12/16 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.

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